1 memory all data sheets are subject to change without notice (858) 503-3300 - fax: (858) 503-3301 - www.maxwell.com p reliminary 3.3v abt16-bit transparent d-type latches 54lvth16373 ?2001 maxwell technologies all rights reserved. 12.19.01 rev 1 1000603 f eatures : ? 3.3v low voltage advanced bicmos technology (lvt) 16- bit transparent d-type latches with 3-state outputs ? total dose hardness: - > 100 krad (si), dependent upon space mission ? single event effect: - sel th : no lu > 119 mev/mg/cm 2 ? package: 48 pin r ad -p ak ? flat package ? operating temperature range: - 55 to 125c ? distributed v cc and gnd pin configuration minimizes high- speed switching noise ? supports mixed-mode signal operation - 5v input and output voltages with 3.3v v cc ? supports unregulated battery operation down to 2.7v ?typical v olp (output ground bounce) < 0.8v at v cc =3.3v, t a =25c ? latch-up performance exceeds 500ma per jedec stan- dard ? supports live insertion ? bus-hold data inputs eliminate the need for external pullup resistors d escription : maxwell technologies? 54lvth16373 16-bit transparent d- type latches with 3-state output features a greater than 100 krad (si) total dose tolerance, dependent upon space mission. the 54lvth16373 is designed for low voltage (3.3v) v cc operation, but with the capability to provide a ttl interface to a 5v system environment. it is suitable for implementing buffer registers, i/o ports, bidirecti onal bus drivers, and working reg- isters. the 54lvth16373 can be us ed as two 8-bit latches or one 16-bit latch. when the latch-enable (le) input is low, the q output are latched at the levels set up at the data (d) inputs. when le is high, the q outputs follow the d inputs. a buffered output-enable (oe ) input can be used to place the eight out- puts in either a normal logic state or a high impedance state. in the high impedance state, the outputs neither load nor drive the bus lines significantly. the high impedance state and the increased drive provide the capabili ty to drive bus lines with- out the need for interface or pullup components. oe does not affect internal operations of the latch. old data can be retained or new data can be entered while the outputs are in the high impedance state. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s. 148 24 25 1le 1d1 1d2 gnd 1d3 1d4 vcc 1d5 1d6 gnd 1d7 1d8 2d1 2d2 gnd 2d3 2d4 vcc 2d5 2d6 gnd 2d7 2d8 2le 2oe 2q8 2q7 gnd 2q6 2q5 vcc 2q4 2q3 gnd 2q2 2q1 1q8 1q7 gnd 1q6 1q5 vcc 1q4 1q3 gnd 1q2 1q1 1oe 1oe/2oe 1le/2le 1d1/2d1 c1 1d 1/24 48/25 47/36 2/13 1q1/2q1 to seven other channels logic diagram (positivelogic ) 54lvth16373 logic diagram
memory p reliminary 2 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 t able 1. p inout d escription p in s ymbol d escription 1, 24 1oe -2oe output enable 2, 3, 5, 6, 8, 9, 11, 12 1q1-1q8 outputs 4, 10, 15, 21, 28, 34, 39, 45 gnd ground 7, 31, 42 v cc power supply 13, 14, 16, 17, 19, 20, 22, 23 2q1-2q8 outputs 25, 48 2le-1le latch enable 26, 27, 29, 30, 32, 31, 32, 33, 35, 36 2d8-2d1 inputs 37, 38, 40, 41, 43, 44, 46, 47 1d8-1d1 inputs t able 2. 54lvth16373 a bsolute m aximum r atings p arameter s ymbol m in m ax u nit supply voltage range v cc -0.5 4.6 v input voltage range 1 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. v i -0.5 7 v voltage range applied to any output in the high state or power-off state 1 v o -0.5 7 v current into any output in the low state i o -- 96 ma current into any output in the high state 2 2. this current flows only when the output is in the high state and v o > v cc . i o -- 48 ma input clamp current (v i < 0) i ik -- -50 ma output clamp current (v o < o) i ok -- -50 ma maximum power dissipation at ta = 55c 3 3. the maximum package power dissipation is ca lculated using a junction temperature of 150 c and a board trace length of 750 mils. p d -- 0.85 mw storage temperature range t s -65 150 c
memory p reliminary 3 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 t able 3. d elta l imits p arameter v ariation i cc(ol) 10% of specified value in table 5 i cc(oh) 10% of specified value in table 5 i cc(od) 10% of specified value in table 5 t able 4. 54lvth16373 r ecommended o perating c onditions 1 1. unused control inputs must be held high or low to prevent them from floating. p arameter s ymbol m in m ax u nit supply voltage v cc 2.7 3.6 v high-level input voltage v ih 2--v low-level input voltage v il -- 0.8 v input voltage v i -- 5.5 v high-level output current i oh -- -24 ma low-level output current i ol -- 68 ma input transition rise or fall rate (outputs enabled) ? t/ ? v-- 10 ns/v operating free-air temperature t a -55 125 c t able 5. 54lvth16373 dc e lectrical c haracteristics (v cc = 3.3v 10%, t a = -55 to 125 c, unless otherwise specified ) p arameter s ymbol t est c onditions m in m ax u nit input clamp voltage v ik v cc = 2.7 i i = -18ma -- -1.2 v high-level output voltage v oh v cc = 2.7v to 3.6v i oh = -100a v cc -0.2 -- v v cc = 2.7v i oh = -8ma 2.4 -- v cc = 3v, i oh = -32ma 2.0 -- low-level output voltage v ol v cc = 2.7v i ol = 100a -- 0.2 v i ol = 24ma -- 0.5 v cc = 3v i ol = 16ma -- 0.4 i ol = 32ma -- 0.5 input current i i v cc = 0 or 3.6v v i = 5.5v 10 a v cc = 3.6v v i = v cc or gnd control inputs -- 1 v cc = 3.6v v i = v cc data inputs -- 1 v i = 0 -- -5
memory p reliminary 4 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 hold current i i(hold) v cc = 3v v i = 0.8v data inputs 75 -- a v i = 2v -75 -- output disabled leakage current - high i ozh v cc = 3.6v, v o = 3v -- 5 a output disabled leakage current - low i ozl v cc = 3.6v, v o = 0.5v -- -5 a power up current i ozpu 2 v cc = 0 to 1.5v, v o = 0.5v to 3v, oe = don?t care -- 100 a power down current i ozpd 2 v cc = 1.5v to 0, v o = 0.5v to 3v, oe = don?t care -- 100 a supply current i cc v cc = 3.6v i o = 0 v i = v cc or gnd outputs high -- 0.19 ma outputs low -- 5 outputs disabled -- 0.19 delta supply current ? i cc 1 v cc = 3v to 3.6v, one input at v cc -0.6v, other inputs at v cc or gnd -- 0.2 ma input capacitance c i 2 v i = 3v or 0 -- 10 pf input output capacitance c o 2 v o = 3v or 0 -- 15 pf 1. this is the increase in supply current for each input t hat is at the specified ttl voltage level rather than v cc or gnd. 2. guaranteed by design. t able 6. 54lvth16373 ac e lectrical c haracteristics (v cc = 3.3v 10%, t a = -55 to 125 c, unless otherwise specified ) p arameter s ymbol v cc = 3.3v 0.3v v cc = 2.7v u nit m in m ax m in m ax pulse duration, le high t w 3.3 -- 3.3 -- ns setup time, data before le? t su 0.5 -- 0.5 -- ns hold time, data after le? t h 1.8 -- 2 -- ns propagation delay time d to q t plh 2.7 5 -- 5.7 ns t phl 2.9 4.9 -- 5.7 propagation delay time le to q t plh 3.6 6 -- 6.8 ns t phl 4.7 6.9 -- 8.8 output enable time oe to q t pzh 2.9 5.3 -- 6.3 ns t pzl 35.1--5.9 t able 5. 54lvth16373 dc e lectrical c haracteristics (v cc = 3.3v 10%, t a = -55 to 125 c, unless otherwise specified ) p arameter s ymbol t est c onditions m in m ax u nit
memory p reliminary 5 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 f igure 1. l oad c ircuit for o utputs figure note: 1. c l includes probe and jig capacitance. output disable time oe to q t phz 4.3 6.8 -- 7.6 ns t plz 45.8--5.9 t able 7. f unction t able ( each 8- bit section ) inputs output q oe le d l hhh lhll llxq 0 hxxz p arameter m easurement i nformation t est s1 t plh /t phl open t plz /t pzl 6v t phz /t pzh gnd t able 6. 54lvth16373 ac e lectrical c haracteristics (v cc = 3.3v 10%, t a = -55 to 125 c, unless otherwise specified ) p arameter s ymbol v cc = 3.3v 0.3v v cc = 2.7v u nit m in m ax m in m ax
memory p reliminary 6 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 f igure 2. p ulse d uration f igure 3. s etup and h old t imes f igure 4. p ropagation d elay t imes i nverting and n on - inverting o utputs
memory p reliminary 7 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 f igure 5. e nable and d isable t imes l ow - and h igh -l evel e nabling f igure n otes : 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. all input pulses are supplied by generators having the following characteristics: prr < 10 mhz, zo = 5 ? , tr < 2.5 ns, tf < 2.5 ns. 4. the outputs are measured one at a time with one transition per measurement.
memory p reliminary 8 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 f48-01 note: all dimensions in inches 48 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.144 0.160 0.176 b 0.008 0.010 0.014 c 0.004 0.006 0.007 d -- 0.620 0.640 e 0.370 0.380 0.390 e1 -- -- 0.410 e2 0.200 0.210 0.220 e3 0.075 0.085 -- e 0.025 bsc l 0.275 0.285 0.295 q 0.013 0.019 0.045 s1 0.005 0.018 -- n48
memory p reliminary 9 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 3.3v abt 16-bit transparent d-type latches 54lvth16373 12.19.01 rev 1 1000603 important notice: these data sheets are created using the chip manufacturer?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
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